FY16-1 KEK/Lapis SOI MPW (MX2040)

FY16-1 KEK/Lapis 0.20um SOI CMOS Pixel MPW run (MX2040)

Last update May. 23, 2016

Final Floor Plan

Thank You for Submission!

What's New

May 7, 2016 : Document and gds file of new 20 bit fuse is added. (see --> PDK)
Apr. 28, 2016 : Calibre PEX (Parasitic EXtraction) document and files are added. (see --> Tips)
Apr. 28, 2016: Digital Library designed by Sebastian Glab is placed (see --> Cell Lib)
Apr. 25, 2016: PDK Rel. 0510 is released. (see --> PDK)
Apr. 23, 2016: DFFLIBv1--- Small layout DFF and Counter designs are released. (see --> DFF)
Apr. 8, 2016 : PDK Rel. 0509 is released (revised on Apr. 11),
Apr. 5, 2016 : Comparison of measurement and simulation in Ron and Ioff of Pass Tr logics (see --> Tips)
Mar. 22, 2016: PLDD SPICE models (v.1) are released.(see --> Notes)
Mar. 22, 2016: New Licensed LAPIS_Semi_TOOLS is uploaded.(see --> PDK)
Feb. 5, 2016: Call for MPW run participants

Deadline of expression of interest : Mar. 5, 2016
Fix submission and mask area: Apr. 8, 2016
Deadline of submission : June 10, 2016 (re-extended)
Scheduled delivery of the chips : Oct. 2016

1) Please put chip ID Mark on your chip. (see --> Cell Lib)

2) Please set origin of your chip at the CENTER of your chip.

3) If you want to trace wafer No. and chip location in the wafer, please put 20 bits fuse (fuse_20) on your chip. (see --> PDK)

4) Please put Outer Frame (GDS#64=OF) according to the 7.9 of the Drawing Rule. (from this run, check of Outer frame existence is added to the DRC rule. You can neglect this DRC error except at top cell.)

5) Please name top cell name as 'top_id_name'. For exampl, if your Chip ID is 'JK1' and chip name is 'INT4', top cell name of your chip should be 'top_JK1_INT4'.

Send following data to Yasuo Arai (yasuo.arai@kek.jp) via e-mail or some internet place;

a) GDS file of your chip.

b) top cell name and nickname of your chip.

c) DRC summary file (top_xxxx.drc.summary) and result file (top_xxxx.drc.results)
(If there remain DRC errors, please write the explanation of the error which you accept.)

d) Packaging request and No. of packaged chips you want (default=5) (packaging cost might be charged separately. See --> Price List)

e) your request on wafer type: CZ_n(default)/FZ_n/DSOI_p (Wafer types might be changed depend on the availability). (chips from additional wafer might be charged separately. See --> Price List)

Notes on this MPW run

=== Doping density of LDD region of transistors will be increased from this run to improve radiation hardness and low temperature characteristics. ===
LDD doping node of PMOS becomes 6 times higher, and that of NMOS becomes 2.5 times higher.
Due to this change, drain currect of PMOS will increase. If your design is sensitive to drivng power of PMOS, please use PLDD SPICE model (v.1) to have better matching.
Due to this change, threshold voltages of PMOS transistors will also change a bit. Doping density of PMOS channel region will be fixed to recover the original Vth value. The PLDD SPICE (v.1) does not yet include this fix, so we will release another version of PLDD SPICE model which fix the threshold voltage at beginning of May.
Since the difference is small in NMOS case, there is no change in NMOS SPICE models.
45 degree routing of metal layer is possible, but it must be converted to polygon from path and the cordinate must be on grid. Also be caful that the width of the metal fulfills DRC rule at everywhere.
Relation between GDS layer and Implantations in different wafer.
'BN4' layer is only for Shizuoka Univ. group.
Please neglect 'BP4', 'DTI' and 'ILW' layers.
If you want to use double SOI wafer, please cover your chip with DSREC (Double SOI Recognition) layer. Double SOI related layers are effective only when they are covered by this layer. Please see Drawing Rule section 7.10.
We are planning to process following wafers in this run.
I) SOITEC CZ(n)-SOI (HR1) wafer (~700 Ohm-cm, same as previous run)
II) Shinetsu Low Oxigen(n)-SOI wafer (> 1 kOhm-cm)
III) Shinetsu Low Oxigen(p) Double-SOI wafer (> 1 kOhm-cm)
Caution : Substrate of the Double SOI wafer is p-type.
This run is 5 metal process (use rule files of '..._5m_...').
Location of MIM Capacitor is between M3 and M4 (use mimcap_1p5f). M5 thick metal is good for power/gnd lines.
BOX thickness is 200nm.
You can create round corner. Use 'Create Polygon' -> 'Create Arc' command in Virtuosso.
Dummy metals will be generated by Lapis. If you don't want to put dummy metals, please use no dummy matel layer (#96~100).

PDK

May 7, 2016: New 20 bit Fuse. (manual, gds). If you want to trace wafer number and your chip location within wafer, please put this fuse pattern on your chip in vertical direction.
Apr. 25, 2016 : PDK Rel. 0510_ic61 (Contents, Rel Note, PDK Rel 0510, Documents)
(SPICE parameter of nch/pch core normal-vt st2 is updated, OF(GDS#64) is added to technology file, document for new fuse layout (20 bits) is added)
Apr. 8, 2016 : PDK Rel. 0509_ic61 (Contents, Rel Note, PDK Rel 0509, Documents).
Mar. 22, 2016: New SOI SemiTOOLS of which license is extended to Mar. 31, 2017 are released.
*LAPIS_Semi_TOOLS61_Setup_Guide_English.pdf, LAPIS_Semi_TOOLS61_20170331.tar.gz (for IC6.1)
*LAPIS_Semi_TOOLS_Setup_Guide_English.pdf, LAPIS_Semi_TOOLS_170331.tar.gz, (for IC5.1)).
(You can check the expiration date by enterring 'LMshowtimelimit' in the CIW window.)
Apr. 13, 2015 : PDK Rel. 0508_ic61 (Contents, Rel Note, PDK Rel 0508, Documents). Only Low Temperature SPICE models are changed from Rel0507.
Sep. 12, 2014 : Contact Tree (p.8) is updated (020SOI_022Wiring_forKEK_Drawing_Rule_Rev22_5.pdf)
Sep. 10, 2014 : 1/f model parameters are updated. Please replace relevant files in 02_soi020_kek_LAPIS_Semi_ic61/SIM_PARAM/hspice/Core directory with this.

SPICE

June 14, 2016 : SPICE model of core diode written by A-R-Tec.
Mar. 22, 2016 : PLDD SPICE (v.1) model.
June 25, 2012 : SPICE rev.8 readme.txt (English), readme_core_st_lv_e.txt (English)
June 30, 2009 : How to specify Body-Tie, Source-Tie, and Body-Floating Tr parameters in SPICE (pdf)
June 23, 2009 : Diode model of dio_ppn_io is only supported (Layout & I-V curve)

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Price List

* MPW run Base Price (22 bare chips)

1,200 kYen/2.9x2.9 mm2 chip

2,600 kYen/4.45x4.45 mm2 chip

4,400 kYen/6.0x6.0 mm2 chip

Other size: negotiable

* Additional chips (22 bare chips) from different wafer in the MPW run

250 kYen/2.9x2.9 mm2 chip

500 kYen/6.0x6.0 mm2 chip

Other size: negotiable

* Cost for Packaging

300k Yen up to 5chips
400k Yen up to 10chips
500k Yen up to 15chips
600k Yen up to 20chips
more chips: negotiable

* Additional Wafer run for a single user

'1,300 kYen(process+wafer)' /wafer for HR1(CZn) wafer

'1,320 kYen(process) + 71.5 kYen(wafer)' /wafer for FZn wafer

'1,420 kYen(process) + 150 kYen(wafer)' /wafer for Doubel-SOI wafer

For Japanese user : Consumption Tax will be added to above price.

For Overseas user : Handled by REPIC Co. Ltd. Shipping and handling fee will be added to above price.

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User Cell Libraries

Apr. 28, 2016: Digital Library designed by Sebastian Glab (AGH, Krakow) (Cell List, DigiLib_20120929)
Apr. 23, 2016: D-Flip/Flop designed by Y. Arai (Manual, DFFLIB Library(v.1))
Mar. 13, 2015 : Arai's private I/O library , IOLIB6v4 (Readme, IOLIB6v4.tar.gz, please define as IOLIB6 in cds.lib).
Mar. 13, 2015 : SRAM Cell designed by I. Kurachi (Manual, 48bit_array, dualport_64bit_array, Whole Library)
Sep. 28, 2014 : Please put an ID mark characters like 'IK1' to your chip to identify your chip visually. Your chip ID is assigned here.
The letter should be written by using Metal 5, and preferably placed on upper right corner. Recommended height of the letter is 40 um or more. Examples (gif, gds(included in IOLIB6))
Aug. 20, 2014 : LVDS Driver/Receiver Data Sheet (v0.1) .
June 4, 2012 : If you want to trace wafer number and your chip location within wafer, please put fuse pattern on your chip.(Cel 'ltfuse3' is included in the IOLIB6 or get from here, drawing rule). Please put the fuse in vertical directiuon in your chip like this to ease laser cut. (--> use fuse_20 in PDK)
July 16, 2010 : Lapis I/O Buffer and Power/GND cell Release Note (Japanese, English) . Layouts and data sheets are included in the PDK Documents.

Packaging

Please use following Pad-Pin Wiring assignment as much as possible. If you need different assignment, please provide as the assignment table.

2.9x2.9 mm2 chip (PGA176, ioring29L2_5M5, 96 pads)
2.9x2.9 mm2 chip (PGA176, ioring29_5M5, 112 pads)
4.45 x 4.45 mm2 chip (PGA176, ioring45L2_5M5, 156 pads)
4.45 x 4.45 mm2 chip (PGA176, ioring45_5M5, 176 pads)
6.0x6.0 mm2 chip (PGA176, ioring60L2S_5M5, 176/188 pads)
6.0x6.0 mm2 chip (PGA240, ioring60L2_5M5, 220 pads, v5b)
6.0x6.0 mm2 chip (PGA240, ioring60_5M5, 236 pads, v5b)

Ceramic Package Phot. Cap is not fixed, so that you can illuminate the chip.
Package : PGA-176 package (cavity size 9.5mm), PGA-240 package (cavity size 12mm)

Design Tips (by Y.Arai)

Apr. 28, 2016 : Calibre PEX (Parasitic EXtraction). Rule files are exist in (work dir)/rules/xrc. Document and calview.cellmap file prepared by Ikebe san. Arai's files (calibre_pex.runset, calibre_pex_option.rul).
Apr. 22, 2016 : Virtuoso files (020techfile_replace.txt, 020soi_kek_arai0509.tech, display_arai0509.drf, cds.lib), or replace PC_020umSOI_KEK(Rel0509) file to this (PC_020umSOI_KEK.tar.gz)
Apr. 22, 2016 : An example of SPICE include files (1603selectR0509_typ.inc)
Apr. 5, 2016 : Comparison of measurement and simulation in Ron and Ioff of Pass Tr logics (pdf).
Oct. 14, 2014 : Role of IMB Mask layer (pdf).
Oct. 14, 2014 : Calibre LVS : Method to remove errors for Lapis resistors (pdf)
Oct. 8, 2014 : To reduce leakage current of transistors @Vg=0, set '.option gmindc=1e-24 gmin=1e-24' in SPICE abd use this model.
Aug. 1, 2014: SOI Design Lecture Slides (Install, Schematics, Layout, Tips)
Aug. 1, 2014 : Calibre files (calibre_lvs_option.rul, calibre_lvs.runset, calibre_drc_option.rul, calibre_drc.runset, calibre_antena_drc_5lmG.runset, calibre_antena_drc_5lmSD.runset, calibre_drc_Marea.runset, calibre_drc_logicgen.runset, calibre_drc_gencheck.runset). Please edit to use latest rule files.
Aug. 1, 2014 : An example of a simple pixel (Simple_PIX.tar.gz)
Dec. 29, 2013 : To check the PDK License time limit, enter 'LMshowtimelimit' in the Virtuoso CIW window.
Dec. 4, 2012 : How to convert IC5.1 library to IC6.1 library (pdf).
June 15, 2012 : If you get "WARNING: Invalid PATHCHK request "! POWER": no POWER nets present, operation aborted." in LVS, please add your Power(Gronud) name in the LVS rule file or LVS option file as "LVS POWER NAME myvdd". New option file 'calibre_lvs_option.rul' is available. Set LVS Report Option 'A B C D E' to skip Resistor w & l check.
May 24, 2012 : An example of pixel layout (fpix1) (pdf, fpix.gds.gz)

Q&A's

Mailing List

Please use our mailing list "soicad@ml.post.kek.jp" or "soipix@ml.post.kek.jp" for your questions and comments.
Mailing list help is available by sending a mail which containn 'help' in mail text to "soicad-ctl@ml.post.kek.jp".
You can get past mail index by sending 'index', and get the mail by sending 'get xxx(index number)' to "soicad-ctl@ml.post.kek.jp"

Useful References

Noise measurements and modeling : 2009-11_KEK, 2010.10_ARTec, 2011.07_OKI
FY15-1 MPW run web page
FY14-1 MPW run web page
FY13-2 MPW run web page
FY13-1 MPW run web page
FY12-2 MPW run web page
FY12-1 MPW run web page
FY11-1 MPW run web page
FY10-2 MPW run web page
FY10-1 MPW run web page
FY09-2 MPW run page
FY09-1 MPW run page
FY08 MPW run page
Berkeley BSIM SOI Model Web Page
Berkeley BSIM SOI 3.1 Manual

If you find any problem in this page, please contact to yasuo.arai@kek.jp

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