Last modified Mar. 2, 2007
日時：March 6, 2007(Tue.)10:00 - 17:00
場所：高エネルギー加速器研究機構
3号館セミナーホール(場所が変更になりました）
(KEK Bldg. 3 Seminar Hall)
Topics:
* Pixel/Strip detector Test Results
* Exchange Shuttle Run Design
* TCAD simulation of the Detector
*Radiation Damage
* Industry SOI Technology Trend
* New Ideas
* Colaboration
Workshop Agenda and Slides (Please ask UID and Password to yasuo.arai @ kek.jp)
Agenda(Temporary)
Session 1
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allocated time includes 5min discussion.
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10:00 Opening Remark (Fumihiko Takasaki (KEK, IPNS Director) )
10:10 SOI Detector R&D : Past & Future (Yasuo ARAI (KEK) )
10:40 Oki Fully Depleted SOI Technology for Utra Low Power Applications (Jiro Ida (OKI Electric Industru Co. Ltd.) )
11:20 SOI Strip Test & Design (Toru Tsuboyama (KEK) )
11:50 Front-end circuit design in FD-SOI (Hirokazu Ikeda (JAXA/ISAS) )
12:20 Lunch
Session 2
13:30 SOI Pixel Design : Univ. of Hawaii (video) (Elena Martin (Univ. of Hawaii) )
13:55 SOI Pixel Design : LBL (video) (Peter Denes (LBL) )
14:15 SOI Pixel Design : FNAL/BNL (video) (Grzegorz Deptuth (BNL(FNAL)) )
14:35 Design of High Voltage MOS Transistor using TCAD (Hirokazu Hayashi (OKI Electric Industru Co. Ltd.) )
14:55 SOI Detector Simulation by ENEXSS (Masashi Hazumi (KEK) )
15:25 break
Session 3
15:40 SOI Pixel Design : X-ray Counting Pixel (Yasuo Arai (KEK) )
16:00 SOI Radiation Damage Test & Chip Design (Youichi Ikegami (KEK) )
16:25 Discussion : Future Collaboration (Yasuo Arai (KEK) )
16:45 Summary (Junji Haba (KEK) )